Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - ip verilog

Search list

[VHDL-FPGA-Verilog] dma_0

Description: SOPC系统编译的DMA的Verilog代码-DMA IP core in SOPC
Platform: | Size: 5120 | Author: zy | Hits:

[VHDL-FPGA-Verilog] can_latest.tar

Description: 用Verilog写的CAN协议IP核 已经验证可以使用 -CAN protocol written in Verilog IP core has been verified using
Platform: | Size: 1172480 | Author: 薛鹏举 | Hits:

[VHDL-FPGA-Verilog] FIFOED_UART

Description: CAL_UART核verilog源码，带FIFO，FIFO深度可设置。-fifoed uart ip core. cal_uart.
Platform: | Size: 6144 | Author: 杨胜尧 | Hits:

[VHDL-FPGA-Verilog] 32bit-RISC-CPU-IP

Description: 使用Verilog语言实现的RISC精简指令集CPU IP核，该CPU具有32位数据宽度，5级流水线结构和指令预判和中断处理功能，适合Verilog语言深入学习者参考。-Using the Verilog language implementation of RISC Reduced Instruction Set CPU IP cores, the CPU has a 32-bit data width, 5-stage pipeline structure and instruction pre-judgment and interrupt handling functions for Verilog language learners in depth reference.
Platform: | Size: 33792 | Author: 张秋光 | Hits:

[TCP/IP stack] MAC_verilog

Description: 以太网MAC网卡的Verilog源代码，可以节省TCP/IP协议的设计开发时间。-Verilog source code for Ethernet MAC network card, you can save the TCP/IP protocol design and development time.
Platform: | Size: 125952 | Author: lxk | Hits:

[VHDL-FPGA-Verilog] IP-coreincluding-VHDL-and-Verilog

Description: 芯片设计必须解剖的IP核（包含VHDL和Verilog代码）-The IP core chip design must anatomy (including VHDL and Verilog code)
Platform: | Size: 1180672 | Author: 张磊 | Hits:

[VHDL-FPGA-Verilog] usb

Description: USB的verilog IP模块，经过DesignCompiler综合验证-USB-verilog IP module, comprehensive verification through DesignCompiler
Platform: | Size: 57344 | Author: sj | Hits:

[VHDL-FPGA-Verilog] IIC_core

Description: 上面是IIC_CORE模块，用来实现IIC协议的Verilog的ip核，本人已经应用过，很好用的！-The above is IIC_CORE module used to implement the ip Verilog IIC nuclear agreement, I have applied before, very good use!
Platform: | Size: 2048 | Author: xingzhanpeng | Hits:

[VHDL-FPGA-Verilog] verilog-ip-core

Description: verilog ip核，源代码，ethernet， video_compression_systems-verilog ip core source code, ethernet, video_compression_systems
Platform: | Size: 3798016 | Author: 刘兵 | Hits:

[ARM-PowerPC-ColdFire-MIPS] ARM-Verilog-HDL-IP-CORE

Description: ARM处理器的IP核，用verilog编写的，对处理器和相关的CPU架构知识有很大帮助。-ARM processor IP core, written in verilog processor and CPU architecture knowledge.
Platform: | Size: 74752 | Author: shen jun | Hits:

[VHDL-FPGA-Verilog] Altera-SDRAM_controller-IP-CORE

Description: ALTRA官方提供的SDRAM的控制内核，VHDL和VERILOG版本都有，希望对大家有用-The ALTRA official SDRAM control kernel, VHDL and VERILOG version have the hope that useful
Platform: | Size: 2378752 | Author: mr jiang | Hits:

[VHDL-FPGA-Verilog] ARM-Verilog-HDL-IP-CORE

Description: ARM Verilog HDL IP CORE， ARM IP核，采用verilog编写-ARM Verilog HDL IP CORE, ARM IP core, using verilog write
Platform: | Size: 48128 | Author: xuyanwu | Hits:

[Other] sdr-sdram-verilog

Description: SDRAM IP CORE,ALTERA提供-SDRAM IP CORE,ALTERA
Platform: | Size: 1277952 | Author: wushj | Hits:

[Compress-Decompress algrithms] fpga-jpeg-Verilog

Description: jpeg ip核解码器，可以用来解码jpeg，verilog源代码-jpeg ip core for verilog HDL
Platform: | Size: 109568 | Author: wanghaiwei | Hits:

[VHDL-FPGA-Verilog] 8051core-Verilog

Description: 基于Verilog的 8051 IP核 内含 Testbench-The 8051 IP core based on Verilog
Platform: | Size: 52224 | Author: 程硕 | Hits:

[Other] Xilinx-FIRfilter-iP

Description: Xilinx IP核设计FIR滤波器,调用IP核实现FIR滤波器，相关具体步骤还有Verilog HDL的相关代码-verilog HDL
Platform: | Size: 346112 | Author: 陈旭 | Hits:

[VHDL-FPGA-Verilog] DES_Triple-DES-IP-Cores

Description: Triple DES 密码算法。 利用Xillinx公司的Virtex-II芯片测试了。正常动作。-Triple DES core implementation in verilog. It takes three standard 56 bit keys and 64 bits of data as input and generates a 64 bit encrypted/decrypted result.
Platform: | Size: 70656 | Author: 金铁男 | Hits:

[VHDL-FPGA-Verilog] Altera FFT IP核 使用实例

Description: Verilog，关于如何调用Altera官方的FFT iP核，如何输入和得到输出的实例。
Platform: | Size: 9807 | Author: dumn1234 | Hits:

[USB develop] USB-IPcore-Verilog

Description: USB IP 核设计，Verilog，ISE工程可以打开-USB IP core design, Verilog, ISE project can be opened
Platform: | Size: 5345280 | Author: 赵海峰 | Hits:

[VHDL-FPGA-Verilog] Verilog-IIC-read-MPU6050-Filter

Description: 本代码实现了读MPU6050 三轴6个数据，用其中的GY和AZ、AX结合融合滤波算法，解出X单轴角度，并在黑金开发板的EP4C15F17C8芯片上调试成功，±5°范围内LED灯灭，左右摆动时相应左右灯亮。 顶层模块每隔5ms，发出一个is_read高电平，下面的模块读取一次数据，并计算，更新LED状态。有关计算都用的ip核，占用资源很大。希望对小小小小白有所帮助。 -Verilog codes read 6 axis data of MPU6050, and use GY AZ AX with complementary filtering arithmetic to calculate X axis angle. Codes run at Altera Chip EP4C15F17C8 and set 2 led light if X angle beyond ±5°. Zip includes .v and .doc.
Platform: | Size: 9501696 | Author: 魏溢 | Hits:
« 1 2 3 4 5 6 7 89 10 11 12 13 ... 18 »

CodeBus www.codebus.net